The invention relates to a circuit combining level shift function with gated reset.
Within microprocessors scaling of the power supply voltage occurs for power reduction and reliability reasons. Certain types of circuits are more sensitive to this reduction in voltage such as analog, memory and chip input/output (I/O) and/or receiving/driving circuits. To combat this, many chip designs have added extra power supply domains to use in these sensitive circuits.
If static logic gates are connected normally at the interface between a lower supply voltage VD and a higher supply voltage VC, as VC rises greater than a PFET (P-doped Field Effect Transistor) threshold voltage above VD, the PFET will turn on and a direct current (DC) will flow through the gate connected to VC. This will prevent a good down level on the output node. This problem can be exacerbated with wider gates in which multiple PFETs could be on and leaking DC current. Because of this, so-called level shifter circuits are known to interface between the different voltage supplies.
Thereby a larger operating range of such level shifter circuits towards a low VD and high VC is desired for memories in combination with a better clock to wordline delay tracking and a better wordline pulse width tracking. Further a minimum impact of the clock to wordline delay is desired providing a short circuit delay in combination with a small area impact. Additionally level shifter circuits with more complex functions are desired, allowing a reduction of area and thus power needy devices such as PFET devices.